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# FMULX (vector, by element)

Floating-point Multiply extended (by element).

### Syntax

``` FMULX Vd.T, Vn.T, Vm.Ts[index] ; Vector, half-precision ```

``` FMULX Vd.T, Vn.T, Vm.Ts[index] ; Vector, single-precision and double-precision ```

Where:

`Vd`
Is the name of the SIMD and FP destination register.
`T`

Is an arrangement specifier:

Vector, half-precision
Can be one of `4H` or `8H`.
Vector, single-precision and double-precision
Can be one of `2S`, `4S` or `2D`.
`Vn`
Is the name of the first SIMD and FP source register.
`Ts`

Is an element size specifier:

Vector, half-precision
Must be `H`.
Vector, single-precision and double-precision
Can be one of `S` or `D`.
`index`

Is the element index:

Vector, half-precision
Must be `H:L:M`.
Vector, single-precision and double-precision
Can be one of `H:L` or `H`.
`Vm`
Is the name of the second SIMD and FP source register in the range 0 to 31.

## Architectures supported (vector)

Supported in ARMv8.2 and later.

## Usage

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD and FP register by the specified floating-point value in the second source SIMD and FP register, places the results in a vector, and writes the vector to the destination SIMD and FP register.

Before each multiplication, a check is performed for whether one value is infinite and the other is zero. In this case, if only one of the values is negative, the result is 2.0, otherwise the result is -2.0.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-15 FMULX (Vector, single-precision and double-precision) specifier combinations

`T` `Ts` `index`
2S S 0 to 3
4S S 0 to 3
2D D 0 or 1