MRS (PSR to general-purpose register)
Move the contents of a PSR to a general-purpose register.
- is an optional condition code.
- is the destination register.
is one of:
- on any processor, in any mode.
- deprecated synonym for APSR and for use in Debug state, on any processor except Armv7‑M and Armv6‑M.
- on any processor, except Armv6‑M, Armv7‑M, Armv8‑M Baseline, and Armv8‑M Mainline, in privileged software execution only.
- on Armv6‑M, Armv7‑M, Armv8‑M Baseline, and Armv8‑M Mainline processors only.
- can be any of:
MRS in combination with
part of a read-modify-write sequence for updating a PSR, for example
to change processor mode, or to clear the Q flag.
In process swap code, the programmers’ model state of the
process being swapped out must be saved, including relevant PSR
contents. Similarly, the state of the process being swapped in must
also be restored. These operations make use of
MSR instruction sequences.
You must not attempt to access the SPSR when the processor is in User or System mode. This is your responsibility. The assembler cannot warn you about this, because it has no information about the processor mode at execution time.
Arm deprecates reading the CPSR endianness bit (E) with an
The CPSR execution state bits, other than the E bit, can only be read when the processor is in Debug state, halting debug-mode. Otherwise, the execution state bits in the CPSR read as zero.
The condition flags can be read in any mode on any processor. Use APSR if you are only interested in accessing the condition flags in User mode.
You cannot use PC for
R in A32 instructions. You can use SP for
R in A32 instructions but this is
You cannot use PC or SP for
R in T32 instructions.
This instruction does not change the flags.
This instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.