Signed saturating addition.
is an optional condition code.
is the destination register.
are the registers holding the operands.
QADD instruction adds the values in
. It saturates the result to the signed
range -231 ≤
x ≤ 231-1.
NoteAll values are treated as two’s complement signed integers by this instruction.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
If saturation occurs, this instruction sets the Q flag. To
read the state of the Q flag, use an
The 32-bit instruction is available in A32 and T32.
For the Armv7‑M architecture, the 32-bit T32 instruction is only available in an Arm®v7E-M implementation.
There is no 16-bit version of this instruction in T32.
QADD r0, r1, r9