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UDIV

Unsigned Divide.

Syntax

UDIV{cond} {Rd}, Rn, Rm

where:

cond
is an optional condition code.
Rd
is the destination register.
Rn
is the register holding the value to be divided.
Rm
is a register holding the divisor.

Register restrictions

PC or SP cannot be used for Rd, Rn, or Rm.

Architectures

This 32-bit T32 instruction is available in Arm®v7‑R, Armv7‑M and Armv8‑M Mainline.

This 32-bit A32 instruction is optional in Armv7‑R.

This 32-bit A32 and T32 instruction is available in Armv7‑A if Virtualization Extensions are implemented, and optional if not.

There is no 16-bit T32 UDIV instruction.

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