FCVTMS (scalar)
Floating-point Convert to Signed integer, rounding toward Minus infinity (scalar).
Syntax
FCVTMS
Wd, Hn ; Half-precision to 32-bit
FCVTMS
Xd, Hn ; Half-precision to 64-bit
FCVTMS
Wd, Sn ; Single-precision to 32-bit
FCVTMS
Xd, Sn ; Single-precision to 64-bit
FCVTMS
Wd, Dn ; Double-precision to 32-bit
FCVTMS
Xd, Dn ; Double-precision to 64-bit
Where:
Wd- Is the 32-bit name of the general-purpose destination register.
Hn- Is the 16-bit name of the SIMD and FP source register.
Xd- Is the 64-bit name of the general-purpose destination register.
Sn- Is the 32-bit name of the SIMD and FP source register.
Dn- Is the 64-bit name of the SIMD and FP source register.
Operation
Floating-point Convert to Signed integer, rounding toward Minus infinity (scalar). This instruction converts the floating-point value in the SIMD and FP source register to a 32-bit or 64-bit signed integer using the Round towards Minus Infinity rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Rd = signed_convertToIntegerExactTowardNegative(Vn)RW or X.