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TLBI

TLB Invalidate operation.

This instruction is an alias of SYS.

The equivalent instruction is SYS #op1, C8, Cm, #op2{, Xt}.

Syntax

TLBI <tlbi_op>{, Xt}

Where:

op1
Is a 3-bit unsigned immediate, in the range 0 to 7.
Cm
Is a name Cm, with m in the range 0 to 15.
op2
Is a 3-bit unsigned immediate, in the range 0 to 7.
<tlbi_op>
Is a TLBI instruction name, as listed for the TLBI system instruction group, and can be one of the values shown in Usage.
Xt
Is the 64-bit name of the optional general-purpose source register, defaulting to 31.

Usage

TLB Invalidate operation. For more information, see A64 system instructions for TLB maintenance in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

The following table shows the valid specifier combinations:

Table 16-11 SYS parameter values corresponding to TLBI operations

<tlbi_op> op1 Cm op2
ALLE1 4 7 4
ALLE1IS 4 3 4
ALLE2 4 7 0
ALLE2IS 4 3 0
ALLE3 6 7 0
ALLE3IS 6 3 0
ASIDE1 0 7 2
ASIDE1IS 0 3 2
IPAS2E1 4 4 1
IPAS2E1IS 4 0 1
IPAS2LE1 4 4 5
IPAS2LE1IS 4 0 5
VAAE1 0 7 3
VAAE1IS 0 3 3
VAALE1 0 7 7
VAALE1IS 0 3 7
VAE1 0 7 1
VAE1IS 0 3 1
VAE2 4 7 1
VAE2IS 4 3 1
VAE3 6 7 1
VAE3IS 6 3 1
VALE1 0 7 5
VALE1IS 0 3 5
VALE2 4 7 5
VALE2IS 4 3 5
VALE3 6 7 5
VALE3IS 6 3 5
VMALLE1 0 7 0
VMALLE1IS 0 3 0
VMALLS12E1 4 7 6
VMALLS12E1IS 4 3 6
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