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# FMULX (scalar, by element)

Floating-point Multiply extended (by element).

### Syntax

``` FMULX Hd, Hn, Vm.H[index] ; Scalar, half-precision ```

``` FMULX Vd, Vn, Vm.Ts[index] ; Scalar, single-precision and double-precision ```

Where:

`Hd`
Is the 16-bit name of the SIMD and FP destination register.
`Hn`
Is the 16-bit name of the first SIMD and FP source register.
`Vm`

The value depends on the instruction variant:

Scalar, half-precision
For the half-precision variant: is the name of the second SIMD and FP source register, in the range V0 to V15
Scalar, single-precision and double-precision
For the single-precision and double-precision variant: is the name of the second SIMD and FP source register in the range 0 to 31.
`V`
Is a width specifier, and can be either `S` or `D`.
`d`
Is the number of the SIMD and FP destination register.
`n`
Is the number of the first SIMD and FP source register.
`Ts`
Is an element size specifier, and can be either `S` or `D`.
`index`

Is the element index, in the range 0 to 7.

For the single-precision and double-precision variant: is the element index H:L, H.

## Architectures supported (scalar)

Supported in ARMv8.2 and later.

## Usage

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD and FP register by the specified floating-point value in the second source SIMD and FP register, places the results in a vector, and writes the vector to the destination SIMD and FP register.

If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 19-9 FMULX (Scalar, single-precision and double-precision) specifier combinations

`V` `Ts` `index`
S S 0 to 3
D D 0 or 1