Floating-point Reciprocal Step.
Hm ; Scalar half precision
m ; Scalar single-precision and double-precision
- Is the 16-bit name of the SIMD and FP destination register.
- Is the 16-bit name of the first SIMD and FP source register.
- Is the 16-bit name of the second SIMD and FP source register.
Is a width specifier, and can be either
- Is the number of the SIMD and FP destination register.
- Is the number of the first SIMD and FP source register.
- Is the number of the second SIMD and FP source register.
Architectures supported (scalar)
Supported in the Arm®v8.2 architecture and later.
Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD and FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD and FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.