FCMEQ (vector, register)
Floating-point Compare Equal (vector).
T ; Vector half precision
T ; Vector single-precision and double-precision
- Is the name of the SIMD and FP destination register.
Is an arrangement specifier:
- Vector half precision
Can be one of
- Vector single-precision and double-precision
Can be one of
- Is the name of the first SIMD and FP source register.
- Is the name of the second SIMD and FP source register.
Architectures supported (vector)
Supported in the Arm®v8.2 architecture and later.
Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD and FP register, with the corresponding floating-point value from the second source SIMD and FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD and FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD and FP register to zero.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.