FCVTAS (vector)
Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector).
Syntax
FCVTAS
Vd.T, Vn.T ; Vector half precision
FCVTAS
Vd.T, Vn.T ; Vector single-precision and double-precision
Where:
Vd- Is the name of the SIMD and FP destination register
T-
Is an arrangement specifier:
- Vector half precision
-
Can be one of
4Hor8H. - Vector single-precision and double-precision
-
Can be one of
2S,4Sor2D.
Vn- Is the name of the SIMD and FP source register
Architectures supported (vector)
Supported in the Arm®v8.2 architecture and later.
Usage
Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD and FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.