FCVTZS (vector, integer)
Floating-point Convert to Signed integer, rounding toward Zero (vector).
T ; Vector half precision
T ; Vector single-precision and double-precision
- Is the name of the SIMD and FP destination register
Is an arrangement specifier:
- Vector half precision
Can be one of
- Vector single-precision and double-precision
Can be one of
- Is the name of the SIMD and FP source register
Architectures supported (vector)
Supported in the Arm®v8.2 architecture and later.
Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD and FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.