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FMLSL, (vector)

Floating-point fused Multiply-Subtract Long from accumulator (vector).

Syntax

FMLSL Vd.Ta, Vn.Tb, Vm.Tb ; FMLSL

FMLSL2 Vd.Ta, Vn.Tb, Vm.Tb ; FMLSL2

Where:

Vd
Is the name of the SIMD and FP destination register
Ta
Is an arrangement specifier, and can be one of 2S or 4S.
Vn
Is the name of the first SIMD and FP source register
Tb
Is an arrangement specifier, and can be one of 2H or 4H.
Vm
Is the name of the second SIMD and FP source register

Architectures supported (vector)

Supported in Arm®v8.2 and later.

Usage

Floating-point fused Multiply-Subtract Long from accumulator (vector). This instruction negates the values in the vector of one SIMD and FP register, multiplies these with the corresponding values in another vector, and accumulates the product to the corresponding vector element of the destination SIMD and FP register. The instruction does not round the result of the multiply before the accumulation.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.

Note

ID_AA64ISAR0_EL1.FHM indicates whether this instruction is supported. See ID_AA64ISAR0_EL1 in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
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