VFMAL (by scalar)
Vector Floating-point Multiply-Add Long to accumulator (by scalar).
index] ; 64-bit SIMD vector
index] ; 128-bit SIMD vector FP/SIMD registers (A32)
- Is the 64-bit name of the SIMD and FP destination register.
- Is the 32-bit name of the first SIMD and FP source register.
- Is the 32-bit name of the second SIMD and FP source register.
Depends on the instruction variant:
- For the 64-bit SIMD vector variant: is the element index in the range 0 to 1.
- For the 128-bit SIMD vector variant: is the element index in the range 0 to 3.
- Is an optional instruction width specifier. See Instruction width specifiers.
- Is the 128-bit name of the SIMD and FP destination register.
- Is the 64-bit name of the first SIMD and FP source register.
- Is the 64-bit name of the second SIMD and FP source register.
Supported in Arm®v8.2 and later.
Vector Floating-point Multiply-Add Long to accumulator (by scalar). This instruction multiplies the vector elements in the first source SIMD and FP register by the specified value in the second source SIMD and FP register, and accumulates the product to the corresponding vector element of the destination SIMD and FP register. The instruction does not round the result of the multiply before the accumulation.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.