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VFMSL (vector)

Vector Floating-point Multiply-Subtract Long from accumulator (vector).

Syntax

VFMSL{q}.F16 Dd, Sn, Sm ; 64-bit SIMD vector

VFMSL{q}.F16 Qd, Dn, Dm ; 128-bit SIMD vector FP/SIMD registers (A32)

Where:

Dd
Is the 64-bit name of the SIMD and FP destination register.
Sn
Is the 32-bit name of the first SIMD and FP source register.
Sm
Is the 32-bit name of the second SIMD and FP source register.
q
Is an optional instruction width specifier. See Instruction width specifiers.
Qd
Is the 128-bit name of the SIMD and FP destination register.
Dn
Is the 64-bit name of the first SIMD and FP source register.
Dm
Is the 64-bit name of the second SIMD and FP source register.

Architectures supported

Supported in Arm®v8.2 and later.

Usage

Vector Floating-point Multiply-Subtract Long from accumulator (vector). This instruction negates the values in the vector of one SIMD and FP register, multiplies these with the corresponding values in another vector, and accumulates the product to the corresponding vector element of the destination SIMD and FP register. The instruction does not round the result of the multiply before the accumulation.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.

Note

ID_ISAR6.FHM indicates whether this instruction is supported.
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