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A32/T32 Instruction Set Reference

Table of Contents

Condition Codes
Conditional instructions
Conditional execution in A32 code
Conditional execution in T32 code
Condition flags
Updates to the condition flags in A32/T32 code
Floating-point instructions that update the condition flags
Carry flag
Overflow flag
Condition code suffixes
Condition code suffixes and related flags
Comparison of condition code meanings in integer and floating-point code
Benefits of using conditional execution in A32 and T32 code
Example showing the benefits of conditional instructions in A32 and T32 code
Optimization for execution speed
A32 and T32 Instructions
A32 and T32 instruction summary
Instruction width specifiers
Flexible second operand (Operand2)
Syntax of Operand2 as a constant
Syntax of Operand2 as a register with optional shift
Shift operations
Saturating instructions
ADC
ADD
ADR (PC-relative)
ADR (register-relative)
AND
ASR
B
BFC
BFI
BIC
BKPT
BL
BLX, BLXNS
BX, BXNS
BXJ
CBZ and CBNZ
CDP and CDP2
CLREX
CLZ
CMP and CMN
CPS
CRC32
CRC32C
CSDB
DBG
DMB
DSB
EOR
ERET
ESB
HLT
HVC
ISB
IT
LDA
LDAEX
LDC and LDC2
LDM
LDR (immediate offset)
LDR (PC-relative)
LDR (register offset)
LDR (register-relative)
LDR, unprivileged
LDREX
LSL
LSR
MCR and MCR2
MCRR and MCRR2
MLA
MLS
MOV
MOVT
MRC and MRC2
MRRC and MRRC2
MRS (PSR to general-purpose register)
MRS (system coprocessor register to general-purpose register)
MSR (general-purpose register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL
MVN
NOP
ORN (T32 only)
ORR
PKHBT and PKHTB
PLD, PLDW, and PLI
POP
PUSH
QADD
QADD8
QADD16
QASX
QDADD
QDSUB
QSAX
QSUB
QSUB8
QSUB16
RBIT
REV
REV16
REVSH
RFE
ROR
RRX
RSB
RSC
SADD8
SADD16
SASX
SBC
SBFX
SDIV
SEL
SETEND
SETPAN
SEV
SEVL
SG
SHADD8
SHADD16
SHASX
SHSAX
SHSUB8
SHSUB16
SMC
SMLAxy
SMLAD
SMLAL
SMLALD
SMLALxy
SMLAWy
SMLSD
SMLSLD
SMMLA
SMMLS
SMMUL
SMUAD
SMULxy
SMULL
SMULWy
SMUSD
SRS
SSAT
SSAT16
SSAX
SSUB8
SSUB16
STC and STC2
STL
STLEX
STM
STR (immediate offset)
STR (register offset)
STR, unprivileged
STREX
SUB
SUBS pc, lr
SVC
SWP and SWPB
SXTAB
SXTAB16
SXTAH
SXTB
SXTB16
SXTH
SYS
TBB and TBH
TEQ
TST
TT, TTT, TTA, TTAT
UADD8
UADD16
UASX
UBFX
UDF
UDIV
UHADD8
UHADD16
UHASX
UHSAX
UHSUB8
UHSUB16
UMAAL
UMLAL
UMULL
UQADD8
UQADD16
UQASX
UQSAX
UQSUB8
UQSUB16
USAD8
USADA8
USAT
USAT16
USAX
USUB8
USUB16
UXTAB
UXTAB16
UXTAH
UXTB
UXTB16
UXTH
WFE
WFI
YIELD
Advanced SIMD Instructions (32-bit)
Summary of Advanced SIMD instructions
Summary of shared Advanced SIMD and floating-point instructions
Interleaving provided by load and store element and structure instructions
Alignment restrictions in load and store element and structure instructions
FLDMDBX, FLDMIAX
FSTMDBX, FSTMIAX
VABA and VABAL
VABD and VABDL
VABS
VACLE, VACLT, VACGE and VACGT
VADD
VADDHN
VADDL and VADDW
VAND (immediate)
VAND (register)
VBIC (immediate)
VBIC (register)
VBIF
VBIT
VBSL
VCADD
VCEQ (immediate #0)
VCEQ (register)
VCGE (immediate #0)
VCGE (register)
VCGT (immediate #0)
VCGT (register)
VCLE (immediate #0)
VCLS
VCLE (register)
VCLT (immediate #0)
VCLT (register)
VCLZ
VCMLA
VCMLA (by element)
VCNT
VCVT (between fixed-point or integer, and floating-point)
VCVT (between half-precision and single-precision floating-point)
VCVT (from floating-point to integer with directed rounding modes)
VCVTB, VCVTT (between half-precision and double-precision)
VDUP
VEOR
VEXT
VFMA, VFMS
VFMAL (by scalar)
VFMAL (vector)
VFMSL (by scalar)
VFMSL (vector)
VHADD
VHSUB
VLDn (single n-element structure to one lane)
VLDn (single n-element structure to all lanes)
VLDn (multiple n-element structures)
VLDM
VLDR
VLDR (post-increment and pre-decrement)
VLDR pseudo-instruction
VMAX and VMIN
VMAXNM, VMINNM
VMLA
VMLA (by scalar)
VMLAL (by scalar)
VMLAL
VMLS (by scalar)
VMLS
VMLSL
VMLSL (by scalar)
VMOV (immediate)
VMOV (register)
VMOV (between two general-purpose registers and a 64-bit extension register)
VMOV (between a general-purpose register and an Advanced SIMD scalar)
VMOVL
VMOVN
VMOV2
VMRS
VMSR
VMUL
VMUL (by scalar)
VMULL
VMULL (by scalar)
VMVN (register)
VMVN (immediate)
VNEG
VORN (register)
VORN (immediate)
VORR (register)
VORR (immediate)
VPADAL
VPADD
VPADDL
VPMAX and VPMIN
VPOP
VPUSH
VQABS
VQADD
VQDMLAL and VQDMLSL (by vector or by scalar)
VQDMULH (by vector or by scalar)
VQDMULL (by vector or by scalar)
VQMOVN and VQMOVUN
VQNEG
VQRDMULH (by vector or by scalar)
VQRSHL (by signed variable)
VQRSHRN and VQRSHRUN (by immediate)
VQSHL (by signed variable)
VQSHL and VQSHLU (by immediate)
VQSHRN and VQSHRUN (by immediate)
VQSUB
VRADDHN
VRECPE
VRECPS
VREV16, VREV32, and VREV64
VRHADD
VRSHL (by signed variable)
VRSHR (by immediate)
VRSHRN (by immediate)
VRINT
VRSQRTE
VRSQRTS
VRSRA (by immediate)
VRSUBHN
VSDOT (vector)
VSDOT (by element)
VSHL (by immediate)
VSHL (by signed variable)
VSHLL (by immediate)
VSHR (by immediate)
VSHRN (by immediate)
VSLI
VSRA (by immediate)
VSRI
VSTM
VSTn (multiple n-element structures)
VSTn (single n-element structure to one lane)
VSTR
VSTR (post-increment and pre-decrement)
VSUB
VSUBHN
VSUBL and VSUBW
VSWP
VTBL and VTBX
VTRN
VTST
VUDOT (vector)
VUDOT (by element)
VUZP
VZIP
Floating-point Instructions (32-bit)
Summary of floating-point instructions
VABS (floating-point)
VADD (floating-point)
VCMP, VCMPE
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (from floating-point to integer with directed rounding modes)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VCVTB, VCVTT (between half-precision and double-precision)
VDIV
VFMA, VFMS, VFNMA, VFNMS (floating-point)
VJCVT
VLDM (floating-point)
VLDR (floating-point)
VLDR (post-increment and pre-decrement, floating-point)
VLLDM
VLSTM
VMAXNM, VMINNM (floating-point)
VMLA (floating-point)
VMLS (floating-point)
VMOV (floating-point)
VMOV (between one general-purpose register and single precision floating-point register)
VMOV (between two general-purpose registers and one or two extension registers)
VMOV (between a general-purpose register and half a double precision floating-point register)
VMRS (floating-point)
VMSR (floating-point)
VMUL (floating-point)
VNEG (floating-point)
VNMLA (floating-point)
VNMLS (floating-point)
VNMUL (floating-point)
VPOP (floating-point)
VPUSH (floating-point)
VRINT (floating-point)
VSEL
VSQRT
VSTM (floating-point)
VSTR (floating-point)
VSTR (post-increment and pre-decrement, floating-point)
VSUB (floating-point)
A32/T32 Cryptographic Algorithms
A32/T32 Cryptographic instructions
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