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Cross trigger register summary

This section describes the cross trigger registers in the Cortex-A72 processor.

These registers are accessed through the internal memory-mapped interface or the external debug interface.

The following table shows the cross trigger registers in the Cortex-A72 processor.

Table 12-3 Cross trigger register summary

Offset Name Type Width Description
0x000 CTICONTROL RW 32-bit CTI Control register 
0x000-0x00C - - - Reserved
0x010 CTIINTACK WO 32-bit CTI Output Trigger Acknowledge register a
0x014 CTIAPPSET RW 32-bit CTI Application Trigger Set register a
0x018 CTIAPPCLEAR WO 32-bit CTI Application Trigger Clear register a
0x01C CTIAPPPULSE WO 32-bit CTI Application Pulse register a
0x020 CTIINEN0 RW 32-bit CTI Input Trigger to Output Channel Enable registers a
0x024 CTIINEN1
0x028 CTIINEN2
0x02C CTIINEN3
0x030 CTIINEN4
0x034 CTIINEN5
0x038 CTIINEN6
0x03C CTIINEN7
0x040-0x09C - - - Reserved
0x0A0 CTIOUTEN0 RW 32-bit CTI Input Channel to Output Trigger Enable registers a
0x0A4 CTIOUTEN1
0x0A8 CTIOUTEN2
0x0AC CTIOUTEN3
0x0B0 CTIOUTEN4
0x0B4 CTIOUTEN5
0x0B8 CTIOUTEN6
0x0BC CTIOUTEN7
0x0C0-0x12C - - - Reserved
0x130 CTITRIGINSTATUS RO 32-bit CTI Trigger In Status register a
0x134 CTITRIGOUTSTATUS RO 32-bit CTI Trigger Out Status register a
0x138 CTICHINSTATUS RO 32-bit CTI Channel In Status register a
0x13C CTICHOUTSTATUS RO 32-bit CTI Channel Out Status register a
0x140 CTIGATE RW 32-bit CTI Channel Gate Enable register a
0x144-0xED8 - - - Reserved
0xEDC CTIITCHINACK WO 32-bit CTI Integration Test Channel In Acknowledge register
0xEE0 CTIITTRIGINACK WO 32-bit CTI Integration Test Trigger In Acknowledge register
0xEE4 CTIITCHOUT WO 32-bit CTI Integration Test Channel Out register
0xEE8 CTIITTRIGOUT WO 32-bit CTI Integration Test Trigger Out register
0xEEC CTIITCHOUTACK RO 32-bit CTI Integration Test Channel Out Acknowledge register
0xEF0 CTIITTRIGOUTACK RO 32-bit CTI Integration Test Trigger Out Acknowledge register
0xEF4 CTIITCHIN RO 32-bit CTI Integration Test Channel In register
0xEF8 CTIITTRIGIN RO 32-bit CTI Integration Test Trigger In register
0xEFC-0xF7C - - - Reserved
0xF00 CTIICTRL RW 32-bit CTI Integration Mode Control register
0xF04-0xFAC - - - Reserved
0xFB0 CTILAR WO 32-bit CTI Lock Access Register a
0xFB4 CTILSR RO 32-bit CTI Lock Status Register a
0xFB8 CTIAUTHSTATUS RO 32-bit CTI Authentication Status register a
0xFBC-0xFC4 - - - Reserved
0xFC8 CTIDEVID RO 32-bit CTI Device Identification register
0xFCC CTIDEVTYPE RO 32-bit CTI Device Type register a
0xFD0 CTIPIDR4 RO 32-bit CTI Peripheral Identification Register 4
0xFD4 CTIPIDR5 RO 32-bit CTI Peripheral Identification Register 5-7
0xFD8 CTIPIDR6
0xFDC CTIPIDR7
0xFE0 CTIPIDR0 RO 32-bit CTI Peripheral Identification Register 0
0xFE4 CTIPIDR1 RO 32-bit CTI Peripheral Identification Register 1
0xFE8 CTIPIDR2 RO 32-bit CTI Peripheral Identification Register 2
0xFEC CTIPIDR3 RO 32-bit CTI Peripheral Identification Register 3
0xFF0 CTICIDR0 RO 32-bit CTI Component Identification Register 0
0xFF4 CTICIDR1 RO 32-bit CTI Component Identification Register 1
0xFF8 CTICIDR2 RO 32-bit CTI Component Identification Register 2
0xFFC CTICIDR3 RO 32-bit CTI Component Identification Register 3

This section contains the following subsections:

a See the ARM® Architecture Reference Manual ARMv8 for more information.
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