Watchpoint debug events
In the Cortex-A72 processor, watchpoint debug events are always synchronous. Memory hint instructions and cache clean operations, except
DC IVAC, and
DC IVAU do not generate watchpoint debug events. Store exclusive instructions generate a watchpoint debug event even when the check for the control of exclusive monitor fails.
For watchpoint debug events, the value reported in DFAR is guaranteed to be no lower than the address of the watchpointed location rounded down to a multiple of 16 bytes.