External debug interface
The system can access memory-mapped debug registers through the APB interface.
The APB interface is compliant with the AMBA 3 APB interface.
The following figure shows the debug interface implemented in the Cortex-A72 processor. For more information on these signals, see the ARM® CoreSight™ Architecture Specification.
Figure 10-23 External debug interface, including APBv3 slave port
This section contains the following subsections: