The optional Accelerator Coherency Port (ACP) is implemented as an AXI4 slave interface with the following restrictions:
- 128-bit read and write interfaces.
- ARCACHE and AWCACHE are restricted to Normal, Write-Back,
Read-Write-Allocate, Read-Allocate, Write-Allocate, and No-Allocate memory. ARCACHE and AWCACHE are limited to the values
0b1111. Other values cause a SLVERR response on RRESP or BRESP.
- Exclusive accesses are not supported.
- Barriers are not supported. BRESP indicates global observation of all writes.
- ARSIZE and AWSIZE signals are not present and assume a value
- ARBURST and AWBURST signals are not present and assume a value of INCR.
- ARLOCK and AWLOCK signals are not present.
- ARQOS and AWQOS signals are not present.
- ARLEN and AWLEN are limited to values 0 and 3.
This section contains the following subsections: