Strictly-enforced inclusion property with L1 data caches
The L2 memory system requires support for inclusion between the L1 data caches and the L2 cache. A line that resides in any of the L1 data caches must also reside in the L2 cache. However, the data can differ between the two caches when the L1 cache line is in a dirty state. If another agent, a core in the cluster or another cluster, accesses this line in the L2 then it knows the line is present in the L1 of a processor and then it queries that core for the most recent data.
This strictly-enforced inclusion property has the following benefits:
- Any AXI or CHI ReadClean operation that results in a line being in shared state in the L1 data caches can be returned from the L2 cache. This yields the highest performance for delivering data to a core.
- When powering down the processor, it reduces the time to clean and invalidate the entire L1 data cache.