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ACE supported transfers

For Normal Inner-Cacheable memory transfers initiated from one of the Cortex-A72 processors, the following transfers are supported on the ACE:

  • WRAP 4× 128-bit read transfers.
  • WRAP 4× 128-bit write transfers.

For Normal Non-Cacheable memory transfers initated from one of the Cortex-A72 processors, the following transfers are supported on the ACE:

  • WRAP 4× 128-bit read transfers.
  • WRAP 4× 128-bit write transfers.
  • INCR 1× 128-bit read transfers.
  • INCR 1× 128-bit write transfers.

For Strongly-ordered or Device transactions initiated from one of the Cortex-A72 processors, the following transfers are supported on the ACE:

  • INCR 1× 8-bit read transfers.
  • INCR 1× 16-bit read transfers.
  • INCR 1× 32-bit read transfers.
  • INCR 1× 64-bit read transfers.
  • INCR N (N:1 or 4) 128-bit read transfers.
  • INCR 1× 8-bit write transfers.
  • INCR 1× 16-bit write transfers.
  • INCR 1× 32-bit write transfers.
  • INCR 1× 64-bit write transfers.
  • INCR N (N:1 or 4) 128-bit write transfers.

The following table describes the use of the burst types for Non-Cacheable and Cacheable but not allocated memory attributes.

Table 7-6 Use of WRAP and INCR burst types for Non-Cacheable and Cacheable but not allocated transactions

Burst type

Used by

WRAP

  • Non-Cacheable read transactions, excluding tablewalk or exclusive accesses.
  • Cacheable but not allocated read transactions initiated from one of the Cortex-A72 processors issued on AR-channel.

INCR

  • Non-cacheable tablewalk and exclusive read transactions.
  • Non-Cacheable or Cacheable but not allocated write transactions initiated from one of the Cortex-A72 processors issued on AW-channel.

If there are requests on the ACP interface, the following transfers can be generated on the ACE if comparable requests are received on the ACP:

  • WRAP N 4× 128-bit read transfers.
  • WRAP 4× 128-bit write transfers.
  • INCR 1× 128-bit read transfers.
  • INCR 1× 128-bit write transfers.