L2 Auxiliary Control Register settings
This section describes the recommended performance settings for the Cortex-A72 L2 Auxiliary Control Register in various system configurations.
Evict and WriteEvict transactions indicate that a shareable cache line has been evicted from the master's local caches. The downstream snoop filter can use this information to update its directory to indicate that the issuing master no longer contains a copy of the cache line.
WriteEvict carries data and can be used to allow allocation into a system or Level 3 cache. In general, ARM recommends the following:
- A system that contains a snoop filter enables Evict transactions.
- A system that contains a L3 cache that wants to behave like a victim cache for cache lines in the Unique state enables WriteEvict transactions.
When the Cortex-A72 processor is used with the ARM CCI-400 in an ACE-based system, ARM recommends that you set L2ACTLR_EL1 to 1 to disable Evict transactions. The reset value of L2ACTLR is 0 in Cortex-A72 ACE configurations. WriteEvict transactions are disabled by default in Cortex-A72 ACE configurations.
When the Cortex-A72 processor is used with the ARM CCN-504 in a CHI-based system, no change is required from the default reset value of L2ACTLR_EL1. By default, Cortex-A72 CHI configurations generate WriteEvict transactions for allocating into the CCN-504 L3 cache but do not generate Evict transactions because the CCN-504 snoop filter does not require them.
WriteUnique and WriteLineUnique transactions
If the Cortex-A72 processor is implemented in an ACE-based system that does not contain a snoop filter, enabling WriteUnique and WriteLineUnique transactions might provide a small increase in system performance. To enable WriteUnique and WriteLineUnique transactions, clear L2ACTLR_EL1. The reset value of L2ACTLR is 1.
If the Cortex-A72 processor is implemented in an ACE-based system that does contain a snoop filter or in a CHI based system, no change is recommended from the default value.