Hyp Architectural Feature Trap Register
The HCPTR characteristics are:
- Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to coprocessors other than CP14 and CP15 and to floating-point and Advanced SIMD functionality. The HCPTR also controls the access to this functionality from Hyp mode.
- Usage constraints
The accessibility to the HCPTR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - - - RW RW -
If a bit in the NSACR prohibits a Non-secure access, then the corresponding bit in the HCPTR behaves as RES1 for Non-secure accesses. See the bit descriptions for more information.
The HCPTR is:
- A Banked EL2 register.
- Architecturally mapped to the AArch64 CPTR_EL2 register.
- See the register summary in Table 4-85 c1 register summary.
The following figure shows the HCPTR bit assignments.
Figure 4-90 HCPTR bit assignments
The following table shows the HCPTR bit assignments.
Table 4-126 HCPTR bit assignments
Trap Coprocessor Access Control Register accesses. When this bit is set to 1, any valid Non-secure EL1 accesses to the CPACR is trapped to Hyp mode. The values are:
Trap Trace Access. This value is:
Trap Advanced SIMD use. If NSACR.NSASEDIS is set to 1, this bit behaves as RES1 on Non-secure accesses. The values are:
NoteIf TCP10 and TCP11 are set to 1, then all Advanced SIMD use is trapped to Hyp mode, regardless of the value of this field.
Trap coprocessor 11. The values are:
Trap coprocessor 10. The possible values are:
To access the HCPTR in AArch32 state, read or write the CP15 register with:
MRC p15, 4, <Rt>, c1, c1, 2; Read Hyp Architectural Feature Trap Register MCR p15, 4, <Rt>, c1, c1, 2; Write Hyp Architectural Feature Trap Register