Multiprocessor Affinity Register
The MPIDR characteristics are:
- Provides an additional core identification mechanism for scheduling purposes in a cluster.
- Usage constraints
The accessibility to the MPIDR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - RO RO RO RO RO
The MPIDR is:
- Common to Secure and Non-secure states.
- Architecturally mapped to the AArch64 MPIDR_EL1[31:0] register.
See the register summary in Table 4-84 c0 register summary.
The following figure shows the MPIDR bit assignments.
Figure 4-80 MPIDR bit assignments
The following table shows the MPIDR bit assignments.
Table 4-116 MPIDR bit assignments
Indicates a single processor system, as distinct from core 0 in a cluster. This value is:
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach:
|[23:16]||Cluster ID Aff2||Indicates the value read in at reset, from the CLUSTERIDAFF2 configuration signal. It identifies a Cortex-A72 device in a system with more than one Cortex-A72 device present.|
|[15:8]||Cluster ID Aff1||Indicates the value read in at reset, from the CLUSTERIDAFF1 configuration signal. It identifies a Cortex-A72 device in a system with more than one Cortex-A72 device present.|
Indicates the core number in the Cortex-A72 device. The possible values are:
To access the MPIDR in AArch32 state, read the CP15 registers with:
MRC p15, 0, <Rt>, c0, c0, 5; Read Multiprocessor Affinity Register