System Control Register
The SCTLR characteristics are:
- Purpose
- Provides the top-level control of the system, including its memory system.
- Usage constraints
The accessibility to the SCTLR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - RW RW RW RW RW Control bits in the SCTLR that are not applicable to a VMSA implementation read as the value that most closely reflects that implementation, and ignore writes.
Some bits in the register are read-only. These bits relate to non-configurable features of an implementation, and are provided for compatibility with other versions of the architecture.
Write access to the Secure copy of SCTLR is disabled when the CP15SDISABLE signal is HIGH.
- Configurations
The SCTLR is Banked for Secure and Non-secure states.
The architectural mapping of the SCTLR is:
- The Non-secure SCTLR is mapped to the AArch64 SCTLR_EL1.
- The Secure SCTLR is mapped to the AArch64 SCTLR_EL3.
- Attributes
- See the register summary in Table 4-85 c1 register summary.
The following figure shows the SCTLR bit assignments.
Figure 4-82 SCTLR bit assignments
The following table shows the SCTLR bit assignments.
Table 4-118 SCTLR bit assignments
Bits | Name | Access | Function | ||||
---|---|---|---|---|---|---|---|
[31] | - | - | Reserved, RES0. | ||||
[30] | TE | Banked |
Thumb Exception enable. This bit controls whether exceptions are taken in ARM or Thumb state:
The primary input CFGTE defines the reset value of the TE bit of the Secure Banked register. |
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[29] | AFE | Banked |
Access flag enable. This bit enables use of the AP[0] bit in the translation table descriptors as the Access flag. It also restricts access permissions in the translation table descriptors to the simplified model as described in the ARM® Architecture Reference Manual ARMv8. In the translation table descriptors, AP[0] is:
When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, this bit is UNK/RES1. This bit is permitted to be cached in a TLB. |
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[28] | TRE | Banked |
TEX remap enable. This bit enables remapping of the TEX[2:1] bits for use as two translation table bits that can be managed by the operating system. Enabling this remapping also changes the scheme that describes the memory region attributes in the VMSA. The possible values are:
When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, this bit is UNK/RES1. This bit is permitted to be cached in a TLB. |
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[27:26] | - | - | Reserved, RES0. | ||||
[25] | EE | Banked |
Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups. The values are:
The primary input CFGEND defines the reset value of the EE bit of the Secure Banked register. |
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[24] | - | - | Reserved, RES0. | ||||
[23:22] | - | - | Reserved, RES1. | ||||
[21] | - | - | Reserved, RES0. | ||||
[20] | UWXN | Banked |
Unprivileged write permission implies EL1 Execute Never (XN). You can use this bit to require all memory regions with unprivileged write permissions are treated as XN for accesses from software executing at EL1. Regions with unprivileged write permission are:
This bit is permitted to be cached in a TLB. |
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[19] | WXN | Banked |
Write permission implies Execute Never (XN). You can use this bit to require all memory regions with write permissions are treated as XN. Regions with write permission are:
This bit is permitted to be cached in a TLB. |
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[18] | nTWE | Banked |
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[17] | - | - | Reserved, RES0. | ||||
[16] | nTWI | Banked |
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[15:14] | - | - | Reserved, RES0. | ||||
[13] | V | Banked |
Vectors bit. This bit selects the base address of the exception vectors:
The primary input VINITHI defines the reset value of the V bit of the Secure Banked register. |
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[12] | I | Banked |
Instruction Cache enable. This is a global enable bit for Instruction Caches:
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[11] | - | - | Reserved, RES1. | ||||
[10:9] | - | - | Reserved, RES0. | ||||
[8] | SED | Banked |
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[7] | ITD | Banked |
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[6] | THEE | Banked |
ThumbEE enable. This value is:
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[5] | CP15BEN | Banked |
AArch32 CP15 barrier enable. The values are:
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[4:3] | - | - | Reserved, RES1. | ||||
[2] | C | Banked |
Cache enable. This is a global enable bit for data and unified caches:
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[1] | A | Banked |
Alignment check enable. This is the enable bit for Alignment fault checking:
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[0] | M | Banked |
MMU enable. This is a global enable bit for the EL1 and EL0 stage 1 MMU:
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To access the SCTLR in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c1, c0, 0; Read System Control Register MCR p15, 0, <Rt>, c1, c0, 0; Write System Control Register
To access the SCTLR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, SCTLR_EL1; Read System Control Register MSR SCTLR_EL1, <Xt>; Write System Control Register
To access the SCTLR_EL3 in AArch64 state, read or write the register with:
MRS <Xt>, SCTLR_EL3; Read System Control Register MSR SCTLR_EL3, <Xt>; Write System Control Register