Translation Table Base Control Register
The TTBCR characteristics are:
Controls which Translation Table Base Register defines the base address for a translation table walk required for the stage 1 translation of a memory access from any mode other than Hyp mode in AArch32 state. This register also controls the translation table format and, when using the Long-descriptor translation table format, holds cacheability and shareability information.
The processor does not use the IMPLEMENTATION DEFINED bit, TTBCR, when using the Long-descriptor translation table format, so this bit is RES0.
- Usage constraints
The accessibility to the TTBCR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - RW RW RW RW RW
Write access to the Secure copy of SCTLR is disabled when the CP15SDISABLE signal is HIGH.
The TTBCR is Banked in the Secure and Non-secure states.
The architectural mapping of the TTBCR is:
- The Non-secure TTBCR is mapped to the AArch64 TCR_EL1[31:0] register.
- The Secure TTBCR is mapped to the AArch64 TCR_EL3[31:0] register
- See the register summary in Table 4-85 c1 register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information.
To access the TTBCR in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c2, c0, 2; Read Translation Table Base Control Register MCR p15, 0, <Rt>, c2, c0, 2; Write Translation Table Base Control Register