You copied the Doc URL to your clipboard.

Fault and Exception handling registers

The following table shows the Fault handling registers in AArch32 state.

Table 4-103 Fault and Exception handling registers

Name CRn op1 CRm op2 Type Reset Description
DFSR c5 0 c0 0 RW UNK Data Fault Status Register.
IFSR     1 RW UNK Instruction Fault Status Register. See Instruction Fault Status Register, EL2.
ADFSR     c1 0 RW UNK Auxiliary Data Fault Status Register. See Auxiliary Fault Status Register 0, EL1 and EL3.
AIFSR     1 RW UNK Auxiliary Instruction Fault Status Register. See Auxiliary Fault Status Register 1, EL1 and EL3.
HADFSR   4 c1 0 RW UNK Hyp Auxiliary Data Fault Status Register. See Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
HAIFSR   1 RW UNK Hyp Auxiliary Instruction Fault Status Register. See Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register.
HSR   c2 0 RW UNK Hyp Syndrome Register. See Exception Syndrome Register, EL2.
DFAR c6 0 c0 0 RW UNK Data Fault Address Register. 
IFAR     2 RW UNK Instruction Fault Address Register. a
HDFAR   4 c0 0 RW UNK Hyp Data Fault Address Register. a
HIFAR     2 RW UNK Hyp Instruction Fault Address Register. a
HPFAR     4 RW UNK Hyp IPA Fault Address Register. a
VBAR c12 0 c0 0 RW 0x00000000b Vector Base Address Register. a
MVBAR     1 RW UNK Monitor Vector Base Address Register. a
RMR     2 RW 0x00000000c Reset Management Register. See Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register.
ISR     c1 0 RO UNK Instruction Status Register. a
HVBAR   4 c0 2 RW UNK Hyp Vector Base Address Register. a

The Virtualization registers include additional fault handling registers. For more information see Virtualization registers.

a See the ARM® Architecture Reference Manual ARMv8 for more information.
b The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.
c The reset value of bit[0] depends on the AA64nAA32 signal. Table 4-103 Fault and Exception handling registers assumes this signal is LOW.
Was this page helpful? Yes No