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Auxiliary Control Register, EL3

The ACTLR_EL3 characteristics are:

Purpose
Enables access to the control registers for the L2 cache and the processor control registers. ACTLR_EL3 is used in conjunction with the ACTLR_EL2 register.
Usage constraints

The accessibility to the ACTLR_EL3 in AArch64 state by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - - RW RW

The accessibility to the ACTLR in AArch32 state by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations

The ACTLR_EL3 is:

  • A Banked register.
  • Mapped to the Secure AArch32 ACTLR register.
Attributes
See the register summary in Table 4-4 AArch64 other System registers.

The following figure shows the ACTLR_EL3 bit assignments.

Figure 4-35 ACTLR_EL3 bit assignments


The following table shows the ACTLR_EL3 bit assignments.

Table 4-51 ACTLR_EL3 bit assignments

Bits Name Function
[31:7] - Reserved, RES0.
[6] L2ACTLR

L2 Auxiliary Control Register. The possible values are:

0The register is not accessible from a lower Exception level. This is the reset value.
1The register is accessible from a lower Exception level.
[5] L2ECTLR

L2 Extended Control Register. The possible values are:

0The register is not accessible from a lower Exception level. This is the reset value.
1The register is accessible from a lower Exception level.
[4] L2CTLR

L2 Control Register. The possible values are:

0The register is not accessible from a lower Exception level. This is the reset value.
1The register is accessible from a lower Exception level.
[3:2] - Reserved, RES0.
[1] CPUECTLR

CPU Extended Control Register. The possible values are:

0The register is not accessible from a lower Exception level. This is the reset value.
1The register is accessible from a lower Exception level.
[0] CPUACTLR

CPU Auxiliary Control Register. The possible values are:

0The register is not accessible from a lower Exception level. This is the reset value.
1The register is accessible from a lower Exception level.

To access the ACTLR_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, ACTLR_EL3; Read Auxiliary Control Register
MSR ACTLR_EL3, <Xt>; Write Auxiliary Control Register

To access the ACTLR in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 1; Read Auxiliary Control Register
MCR p15, 0, <Rt>, c1, c0, 1; Write Auxiliary Control Register

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