About system control
The System registers control and provide status information for the functions implemented in the processor.
The main functions of the System registers are:
- Overall system control and configuration.
- Memory Management Unit (MMU) configuration and management.
- Cache configuration and management.
- System performance monitoring.
- Generic Interrupt Controller (GIC) configuration and management.
The System registers are accessible in AArch32 and AArch64 states. The Execution states are described in the ARMv8-A architecture concepts. The System register access in AArch64 state is characterized by three possible scenarios. These scenarios are:
- The AArch64 register is unique and described for the AArch64 state in AArch64 register descriptions.
- The AArch64 register is architecturally mapped to an AArch32 register but has different bit or bit field assignments. There a separate descriptions for each Execution state in AArch64 register descriptions and AArch32 register descriptions.
- The AArch64 register is architecturally mapped to an AArch32 register with the same bit and bit field assignments. There is one description for both Execution states in the AArch64 register descriptions and cross-referenced from the AArch32 register summary.
The System registers accessed in AArch32 state are described in the AArch32 register descriptions.
Some of the System registers can be accessed through the memory-mapped or external debug interfaces.
Bits in the System registers that are described in the ARMv7 architecture are redefined in the ARMv8-A architecture:
- UNK/SBZP, RAZ/SBZP, and RAZ/WI are redefined as RES0.
- UNK/SBOP and RAO/SBOP are redefined as RES1.
RES0 and RES1 are described in the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
This section contains the following subsections: