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ARM Cortex-A72 MPCore Processor Technical Reference Manual : ROM table Debug Component Identification Registers

ROM table Debug Component Identification Registers

There are four read-only Component Identification Registers, Component ID0 through Component ID3. The following table shows these registers.

Table 10-39 Summary of the ROM table Debug Component Identification registers

Register Value Offset
ROMCIDR0 0x0D 0xFF0
ROMCIDR1 0x10 0xFF4
ROMCIDR2 0x05 0xFF8
ROMCIDR3 0xB1 0xFFC

The ROM table Debug Component Identification Registers identify Debug as an ARM Debug Interface v5 component. The ROM table Component ID registers are:

ROM table Debug Component Identification Register 0

The ROMCIDR0 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11-1 External register access conditions describes the access conditions.

Configurations
The ROMCIDR0 is in the Debug power domain.
Attributes
See the register summary in Table 10-30 ROM table registers.

The following figure shows the ROMCIDR0 bit assignments.

Figure 10-30 ROMCIDR0 bit assignments


The following table shows the ROMCIDR0 bit assignments.

Table 10-40 ROMCIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] PRMBL_0
0x0DPreamble byte 0

ROM table Debug Component Identification Register 1

The ROMCIDR1 characteristics are:

PurposeProvides information to identify an external debug component.
Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11-1 External register access conditions describes the access conditions.

ConfigurationsThe ROMCIDR1 is in the Debug power domain.
AttributesSee the register summary in Table 10-30 ROM table registers.

The following figure shows the ROMCIDR1 bit assignments.

Figure 10-31 ROMCIDR1 bit assignments


The following table shows the ROMCIDR1 bit assignments.

Table 10-41 ROMCIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] CLASS
0x1Component Class. For a ROM table.
[3:0] PRMBL_1
0x0Preamble.

ROM table Debug Component Identification Register 2

The ROMCIDR2 characteristics are:

PurposeProvides information to identify an external debug component.
Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11-1 External register access conditions describes the access conditions.

ConfigurationsThe ROMCIDR2 is in the Debug power domain.
AttributesSee the register summary in Table 10-30 ROM table registers.

The following figure shows the ROMCIDR2 bit assignments.

Figure 10-32 ROMCIDR2 bit assignments


The following table shows the ROMCIDR2 bit assignments.

Table 10-42 ROMCIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] PRMBL_2
0x05Preamble byte 2

ROM table Debug Component Identification Register 3

The ROMCIDR3 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11-1 External register access conditions describes the access conditions.

Configurations
The ROMCIDR3 is in the Debug power domain.
Attributes
See the register summary in Table 10-30 ROM table registers.

The following figure shows the ROMCIDR3 bit assignments.

Figure 10-33 ROMCIDR3 bit assignments


The following table shows the ROMCIDR3 bit assignments.

Table 10-43 ROMCIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] PRMBL_3
0xB1Preamble byte 3
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