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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Memory access sequence

Memory access sequence

When the processor generates a memory access, the MMU:

  1. Performs a lookup for the requested VA, current ASID, current VMID, and memory space in the relevant L1 instruction or data TLB.
  2. Performs a lookup for the requested VA, current ASID, current VMID, and memory space in the unified L2 TLB if there is a miss in the relevant L1 TLB.
  3. Performs a hardware translation table walk if there is a miss in the L2 TLB.

When executing in AArch64 at a particular Exception level, you can configure the hardware translation table walk to use either the 4KB translation granule or the 64KB translation granule. Program the Translation Granule bit, TG0, in the appropriate translation control register:

  • TCR_EL1.
  • TCR_EL2.
  • TCR_EL3.
  • VTCR_EL2.

When executing in AArch32 in a particular mode, you can configure the MMU to perform translation table walks using either the Short Descriptor Translation Table or the Long Descriptor Translation table format, by programming the Extended Address Enable bit, EAE, in the appropriate translation table control register. Only the Long Descriptor Translation format is supported in Hyp mode.

You can configure the MMU to perform translation table walks in Cacheable regions, by programming the IRGN bits:

AArch32
  • Translation table base registers (TTBR0/TTBR1_ELx) when using the Short Descriptor translation table format.
  • TCR_ELx register when using the Long Descriptor translation table format.
AArch64In the appropriate TCR_ELx register.

For Stage2 translations, the IRGN bits must be programmed in the VTCR_EL2 register.

If the encoding of the IRGN bits is WriteBack, an L2 data cache lookup is performed and data is read from the data cache. If the encoding of the IRGN bits is Write-Through or Non-cacheable, an access to external memory is performed.

In the case of an L2TLB miss, the hardware does a translation table walk provided the MMU is enabled, and the translation using the base register has not been disabled by:

  • Setting the PD0 or PD1 bit in the Translation Table Base Control Register, to disallow translation using either TTBR0 or TTBR1 respectively, when using AArch32 along with the Short Descriptor Format.
  • Setting of the EPD0 or EPD1 bit in the TCR_EL1 register when using AArch64 or when using the Long Descriptor format in AArch32.

If the translation table walk is disabled for a particular base register, the processor returns a Translation Fault. If the TLB finds a matching entry, it uses the information in the entry as follows:

  • The access permission bits and the domain, when using the Short Descriptor format in AArch32 state, determine if the access is permitted. If the matching entry does not pass the permission checks, the MMU signals a Permission fault. See the ARM® Architecture Reference Manual ARMv8 for:

    • A description of the various faults.
    • The fault codes.
    • Information regarding the registers where the fault codes are set.
  • The memory region attributes specified in the TLB entry determine if the access is:

    • Secure or Non-secure.

    • Inner, Outer or not Cacheable.
    • Normal Memory or Device type, Strongly-ordered or Device type when using the Short Descriptor Format in AArch32.
    • One of the four different device memory types defined for ARMv8:

      Device-nGnRnEDevice non-Gathering, non-Reordering, No Early Write Acknowledgment.
      Device-nGnREDevice non-Gathering, non-Reordering, Early Write Acknowledgment.
      Device-nGREDevice non-Gathering, Reordering, Early Write Acknowledgment.
      Device-GREDevice Gathering, Reordering, Early Write Acknowledgment.
  • The TLB translates the VA to a PA for the memory access.
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