External register access permissions
External access permission to the PMU registers is subject to the conditions at the time of the access. The following table describes the processor response to accesses through the external debug and memory-mapped interfaces.
Table 11-1 External register access conditions
|Off||EDPRSR.PU is 0||
Core power domain is completely off, or in a low-power state where the Core power domain registers cannot be accessed.
NoteIf debug power is off then all external debug and memory-mapped register accesses return an error.
|DLK||EDPRSR.DLK is 1||OS Double Lock is locked.|
|OSLK||OSLSR_EL1.OSLK is 1||OS Lock is locked.|
||External performance monitors access disabled. When an error is returned because of the EPMAD condition, and this is the highest priority error condition, EDPRSR.SPMAD is set to 1. Otherwise SPMAD is unchanged.|
|SLK||Memory-mapped interface only||Software Lock is locked. For the external debug interface, ignore this condition.|
|Default||-||None of the conditions apply, normal access.|
The following table shows an example of external register access conditions for access to a Performance Monitors register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column whose condition is true, the entry gives the register’s access permission and scanning stops.
Table 11-2 External register access conditions example