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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Power control signals

Power control signals

The following table shows the power control signals.

Table A-6 Power control signals

Signal Type Description
EVENTI Input Event input for processor wake-up from WFE low-power state. When this signal is asserted, it acts as a WFE wake-up event to all the processors in the MPCore device. This signal must be asserted for at least one CLK cycle.
EVENTO Output Event output. This signal is asserted HIGH for three CLK cycles when any of the processors in the MPCore device executes an SEV instruction.
CLREXMONREQ Input Clearing of the external global exclusive monitor request. When this signal is asserted, it acts as a WFE wake-up event to all the processors in the MPCore device.
CLREXMONACK Output Clearing of the external global exclusive monitor acknowledge.
STANDBYWFE[N:0] Output

Indicates whether a processor is in WFE low-power state:

0Processor not in WFE low-power state.
1Processor in WFE low-power state.
STANDBYWFI[N:0] Output

Indicates whether a processor is in WFI low-power state:

0Processor not in WFI low-power state.
1Processor in WFI low-power state.
STANDBYWFIL2 Output

Indicates whether the L2 is in WFI low-power state. This signal is active when the following are true:

  • All processors are in WFI low-power state.
  • ACINACTM or SINACT and AINACTS are asserted HIGH.
  • memory system is idle.
L2FLUSHREQ Input

L2 hardware flush request. This signal indicates:

0L2 hardware flush request is not asserted.
1L2 hardware flush request is asserted.
L2FLUSHDONE Output

L2 hardware flush done.

0L2 hardware flush is not finished.
1L2 hardware flush is finished.
SMPEN[N:0] Output

CPUECTLR.SMPEN output. This signal indicates:

0The CPUECTLR.SMPEN bit is not set.
1The CPUECTLR.SMPEN bit is set.
CPUQACTIVE[N:0] Output When HIGH, it indicates that processor N is active.
CPUQREQn[N:0] Input The power controller sets this signal LOW, to request that processor N enters retention state.
CPUQACCEPTn[N:0] Output This signal goes LOW, if processor N accepts the power controller retention request.
CPUQDENY[N:0] Output When HIGH, it indicates that processor N denies the power controller retention request.
L2QACTIVE Output When HIGH, it indicates that the L2 Data and Tag RAMs are active.
L2QREQn Input The power controller sets this signal LOW, to request that the L2 Data and Tag RAMs enter retention state.
L2QACCEPTn Output This signal goes LOW, if the L2 Data and Tag RAMs accept the power controller retention request.
L2QDENY Output When HIGH, it indicates that the L2 Data and Tag RAMs deny the power controller retention request.
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