Hyp Translation Control Register
The processor does not use the IMPLEMENTATION DEFINED bit, HTCR, so this bit is RES0.
The HTCR characteristics are:
- Controls translation table walks required for the stage 1 translation of memory accesses from Hyp mode, and holds cacheability and shareability information for the accesses.
- Usage constraints
The accessibility to the HTCR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - - - RW RW -
The HTCR is:
- A Banked EL2 register.
- Architecturally mapped to the AArch64 TCR_EL2.
The TCR_EL2 is a 32-bit register in AArch64 state.
- See the register summary in Table 4-85 c1 register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information.
To access the HTCR in AArch32 state, read or write the CP15 register with:
MRC p15, 4, <Rt>, c2, c0, 2; Read Hyp Translation Control Register MCR p15, 4, <Rt>, c2, c0, 2; Write Hyp Translation Control Register