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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Non-secure Access Control Register

Non-secure Access Control Register

The NSACR characteristics are:

Purpose
Defines the Non-secure access permission to the CP10 and CP11 coprocessors and controls Non-secure Advanced SIMD functionality.
Usage constraints

The accessibility to the NSACR by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO TRAP RO RO RW

If EL3 is using AArch64, accesses to this register from Secure EL1 using AArch32 are trapped to EL3.

Configurations

The NSACR:

  • Is a Restricted access register that exists only in the Secure state but can be read from the Non-secure state.
  • Functionality is replaced by the behavior in the CPTR_EL3 register in AArch64 state.

When EL3 is using AArch64, reads of the NSACR from Non-secure EL2 or Non-secure EL1 using AArch32, return a fixed value of 0x00000C00.

Attributes
See the register summary in Table 4-85 c1 register summary.

The following figure shows the NSACR bit assignments.

Figure 4-85 NSACR bit assignments


The following table shows the NSACR bit assignments.

Table 4-121 NSACR bit assignments

Bits Name Function
[31:21] - Reserved, RES0.
[20] NSTRCDIS

Disable Non-secure access to CP14 trace registers:

0CP14 access to trace registers is not supported. This bit is RES0.
[19:16] - Reserved, RES0.
[15] NSASEDIS

Disables Non-secure Advanced SIMD functionality. The values are:

0This bit has no effect on the ability to write to the CAPCR.ASEDIS bit. This is the reset value.
1When executing in Non-secure state, the CPACR.ASEDIS bit is RES1.
[14:12] - Reserved, RES0.
[11] cp11

Non-secure access to coprocessor 11 enable. The values are:

0Secure access only. Any attempt to access coprocessor 11 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.
1Access from any Security state.
[10] cp10

Non-secure access to coprocessor 10 enable. The values are:

0Secure access only. Any attempt to access coprocessor 10 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.
1Access from any Security state.
[9:0] - Reserved, RES0.

To access the NSACR in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c1, 2; Read Non-secure Access Control Register data
MCR p15, 0, <Rt>, c1, c1, 2; Write Non-secure Access Control Register data