Non-secure Access Control Register
The NSACR characteristics are:
- Defines the Non-secure access permission to the CP10 and CP11 coprocessors and controls Non-secure Advanced SIMD functionality.
- Usage constraints
The accessibility to the NSACR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - RO TRAP RO RO RW
If EL3 is using AArch64, accesses to this register from Secure EL1 using AArch32 are trapped to EL3.
- Is a Restricted access register that exists only in the Secure state but can be read from the Non-secure state.
- Functionality is replaced by the behavior in the CPTR_EL3 register in AArch64 state.
When EL3 is using AArch64, reads of the NSACR from Non-secure EL2 or Non-secure EL1 using AArch32, return a fixed value of
- See the register summary in Table 4-85 c1 register summary.
The following figure shows the NSACR bit assignments.
Figure 4-85 NSACR bit assignments
The following table shows the NSACR bit assignments.
Table 4-121 NSACR bit assignments
Disable Non-secure access to CP14 trace registers:
Disables Non-secure Advanced SIMD functionality. The values are:
Non-secure access to coprocessor 11 enable. The values are:
Non-secure access to coprocessor 10 enable. The values are:
To access the NSACR in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c1, c1, 2; Read Non-secure Access Control Register data MCR p15, 0, <Rt>, c1, c1, 2; Write Non-secure Access Control Register data