Primary Region Remap Register
The PRRR characteristics are:
- Controls the top-level mapping of the TEX, C, and B memory region attributes.
- Usage constraints
The accessibility to the PRRR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0) - RW RW RW RW RW
Write access to the Secure copy of PRRR is disabled when the CP15SDISABLE signal is HIGH.
The PRRR is:
- Banked for the Secure and Non-secure states.
- Only relevant if the TTBCR.EAE bit is 0.
- Architecturally mapped to the MAIR0 register in AArch32 state.
The Non-secure PRRR is architecturally mapped to the AArch64 MAIR_EL1[31:0] register.
The Secure PRRR is mapped to the AArch64 MAIR_EL3[31:0] register.
- See the register summary in Table 4-94 c10 register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information.
To access the PRRR in AArch32 state when TTBCR.EAE is 0, read or write the CP15 register with:
MRC p15, 0, <Rt>, c10, c2, 0; Read Primary Region Remap Register MCR p15, 0, <Rt>, c10, c2, 0; Write Primary Region Remap Register