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ARM Cortex-A72 MPCore Processor Technical Reference Manual : c15 registers

c15 registers

The following table shows the System registers when CRn is c15 and the processor is in AArch32 state.

Table 4-98 c15 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 IL1DATA0 RW UNK Instruction L1 Data n Register, EL1.
  1 IL1DATA1
  2 IL1DATA2
  3 IL1DATA3
  c1 0 DL1DATA0 RW UNK Data L1 Data n Register, EL1.
  1 DL1DATA1
  2 DL1DATA2
  3 DL1DATA3
  4 DL1DATA4
  c4 0 RAMINDEXa WO - RAM Index operation.
1 c0 0 L2ACTLR RW 0x00000010b L2 Auxiliary Control Register. See .
  c3 0 CBAR RO -c Configuration Base Address Register.
a RAMINDEX is a system operation.
b The reset value is 0x00000010 for an ACE interface and 0x00004018 for a CHI interface.
c The reset value depends on the primary input, PERIPHBASE[43:18].