CPU Extended Control Register, EL1
The CPUECTLR_EL1 characteristics are:
- Provides additional IMPLEMENTATION DEFINED configuration and control options for the processor.
- Usage constraints
The accessibility to the CPUECTLR_EL1 by Exception level is:
The CPUECTLR_EL1 can be written dynamically.
The CPUECTLR_EL1 is:
- Common to the Secure and Non-secure states.
- 64-bit read/write register.
- Architecturally mapped to the AArch32 CPUECTLR register.
- See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the CPUECTLR_EL1 bit assignments.
Figure 4-75 CPUECTLR_EL1 bit assignments
The following table shows the CPUECTLR_EL1 bit assignments.
Table 4-79 CPUECTLR_EL1 bit assignments
|||Disable table walk descriptor access prefetch||
Disables table walk descriptor access prefetch. The possible values are:
|[36:35]||instruction fetch prefetch distance||
Indicates the L2 instruction fetch prefetch distance. It is the number of requests by which the prefetcher is ahead of the demand request stream. It also specifies the maximum number of prefetch requests generated on a demand miss. The possible values are:
|[33:32]||L2 load data prefetch distance||
Indicates the L2 load data prefetch distance. It is the number of requests by which the prefetch request to the L2, on a load stream, is ahead of the demand request stream. The possible values are:
Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster.
You must set this bit before enabling the caches and MMU, or performing any cache and TLB maintenance operations.
You must clear this bit during a processor power down sequence. See Power management.
The possible values are:
|[2:0]||Processor dynamic retention control||
Processor dynamic retention control. The possible values are:
All other values are reserved.
To access the CPUECTLR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, S3_1_c15_c2_1; Read EL1 CPU Extended Control Register MSR S3_1_c15_c2_1, <Xt>; Write EL1 CPU Extended Control Register
To access the CPUECTLR in AArch32 state, read or write the CP15 register with:
MRRC p15, 1, <Rt>, <Rt2>, c15; Read CPU Extended Control Register MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register