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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Hypervisor System Trap Register

Hypervisor System Trap Register

The HSTR_EL2 characteristics are:

Purpose
Controls trapping to Hyp mode of Non-secure accesses, at EL1 or lower, of use of Jazelle or the CP15 primary coprocessor registers, c0, c1, c2, c3, c5, c6, c7, c8, c9, c10, c11, c12, c13, or c15 in AArch32 state.
Usage constraints

The accessibility to the HSTR_EL2 in AArch64 state by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW

The accessibility to the HSTR in AArch32 state by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW -
Configurations

The HSTR_EL2 is:

  • A Banked EL2 register.
  • Architecturally mapped to AArch32 HSTR register.
Attributes
See the register summary in Table 4-13 AArch64 virtualization registers.

The following figure shows the HSTR_EL2 bit assignments.

Figure 4-33 HSTR_EL2 bit assignments


The following table shows the HSTR_EL2 bit assignments.

Table 4-49 HSTR_EL2 bit assignments

Bits Name Function
[31:17] - Reserved, RES0.
[16] TEEE

Trap ThumbEE. This value is:

0ThumbEE is not supported.
[15] T15

Trap coprocessor primary register CRn = 15. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure accesses to coprocessor primary register CRn = c15 in AArch32 state to Hyp mode.
[14] - Reserved, RES0.
[13] T13

Trap coprocessor primary register CRn = 13. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure accesses to coprocessor primary register CRn = c13 in AArch32 state to Hyp mode.
[12] T12

Trap coprocessor primary register CRn = 12. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure accesses to coprocessor primary register CRn = c12 in AArch32 state to Hyp mode.
[11] T11

Trap coprocessor primary register CRn = 11. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure accesses to coprocessor primary register CRn = c11 in AArch32 state to Hyp mode.
[10] T10

Trap coprocessor primary register CRn = 10. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c10 in AArch32 state to Hyp mode.
[9] T9

Trap coprocessor primary register CRn = 9. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c9 in AArch32 state to Hyp mode.
[8] T8

Trap coprocessor primary register CRn = 8. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c8 in AArch32 state to Hyp mode.
[7] T7

Trap coprocessor primary register CRn = 7. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c7 in AArch32 state to Hyp mode.
[6] T6

Trap coprocessor primary register CRn = 6. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c6 in AArch32 state to Hyp mode.
[5] T5

Trap coprocessor primary register CRn = 5. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c5 in AArch32 state to Hyp mode.
[4] - Reserved, RES0.
[3] T3

Trap coprocessor primary register CRn = 3. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c3 in AArch32 state to Hyp mode.
[2] T2

Trap coprocessor primary register CRn = 2. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c2 in AArch32 state to Hyp mode.
[1] T1

Trap coprocessor primary register CRn = 1. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c1 in AArch32 state to Hyp mode.
[0] T0

Trap coprocessor primary register CRn = 0. The possible values are:

0Has no effect on Non-secure accesses to CP15 coprocessor registers. This is the reset value.
1Trap valid Non-secure EL0 or EL1 accesses to coprocessor primary register CRn = c0 in AArch32 state to Hyp mode.

To access the HSTR_EL2 in AArch64 state, read or write the register with:

MRS <Xt>, HSTR_EL2; Read Hyp System Trap Register
MSR HSTR_EL2, <Xt>; Write Hyp System Trap Register

To access the HSTR in AArch32 state, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c1, 3; Read Hyp System Trap Register
MCR p15, 4, <Rt>, c1, c1, 3; Write Hyp System Trap Register