The following table lists the options that the implementer can choose when implementing the Cortex-A72 processor in an SoC.
Table 1-1 Cortex-A72 processor implementation options
|Feature||Range of options|
|Number of cores||1-4|
|Cryptography engine||Included or Not|
|cache size||512KB, 1MB, 2MB, or 4MB|
|L2 Tag RAM register slice||0 or 1|
|L2 Data RAM register slice||0, 1, or 2|
|L2 arbitration register slice||0 or 1|
|L2 FEQ size||20, 24, or 28 entries|
|Regional gated clock a||Included or Not|
|ECC or parity support||Supported in L1 and L2, L2 only, or none.|
|Bus interface||ACE or CHI|
|ACP||Included or Not|
|GIC CPU interface||Included or Not|
- All the cores share an integrated L2 cache and optional GIC CPU interface. Each core has the same configuration for the Cryptography engine and L1 ECC or parity.
- The optional Cryptography engine is not included in the base product of the Cortex-A72 processor. ARM requires licensees to have contractual rights to obtain the Cortex-A72 processor Cryptography engine.
The L2 Tag RAM register slice option adds register slices to the L2 Tag RAMs. The L2 Data RAM register slice option adds register slices to the L2 Data RAMs. The following table lists valid combinations of the L2 Tag RAM and L2 Data RAM register slice options.
Table 1-2 Valid combinations of L2 Tag and Data RAM register slice
Tag RAM register slice L2 Data RAM register slice 0 0 0 1 1 1 0 2 1 2
- If the L2 arbitration register slice is included then it adds an additional pipeline stage in the processor-L2 arbitration logic interface.
- The Cortex-A72 processor must be configured with a CHI interface to connect to a CHI interconnect.