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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Configuration signals

Configuration signals

The following table shows the configuration signals.

Table A-3 Configuration inputs

Signal Type Description
CFGEND[N:0] Input

Individual core control of the endianness configuration at reset. It sets the initial value of the EE bit in the System Control Register (SCTLR or SCTLR_EL3):

0EE bit is 0.
1EE bit is 1.

This signal is only sampled during powerup reset of the processor.

VINITHI[N:0] Input

Individual core control of the location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 System Control Register (SCTLR when the highest Exception level is AArch32):

0Exception vectors start at address 0x00000000.
1Exception vectors start at address 0xFFFF0000.

This signal is only sampled during powerup reset of the processor.

CFGTE[N:0] Input

Individual core control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register (SCTLR when the highest Exception level is AArch32):

0TE bit is 0.
1TE bit is 1.

This signal is only sampled during powerup reset of the processor.

CP15SDISABLE[N:0] Input Disable write access to some Secure CP15 registers. See  Registers affected by CP15SDISABLE.
CLUSTERIDAFF1[7:0] Input

Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity Register (MPIDR).

This signal is only sampled during powerup reset of the processor.

CLUSTERIDAFF2[7:0] Input

Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity Register (MPIDR).

This signal is only sampled during powerup reset of the processor.

AA64nAA32[N:0] Input

Individual core register width state. The register width states are:

0AArch32.
1AArch64.

This signal is only sampled during powerup reset of the processor.

RVBARADDRx[43:2]a Input Reset Vector Base Address for executing in AArch64 state. This signal is only sampled during reset of the processor.
CRYPTODISABLE[N:0]b Input

Individual core Cryptography engine disable:

0Enable the Cryptography engine.
1Disable the Cryptography engine.

This signal is only sampled during powerup reset of the processor. This signal only exists if the processor implements the Cryptography Extension.

a x is 0, 1, 2, or 3 to reference a specific core.
b The optional Cryptography engine is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Cortex-A72 processor Cryptography engine.
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