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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Cross trigger channel interface

Cross trigger channel interface

The following table shows the cross trigger channel interface signals.

Table A-38 Cross trigger channel interface signals

Signal Type Description
CIHSBYPASS[3:0] Input Cross trigger channel interface handshake bypass.
CISBYPASS Input Cross trigger channel interface sync bypass.
CTICHIN[3:0] Input

Cross trigger channel input. Each bit represents a valid channel input:

0Channel input inactive.
1Channel input active.
CTICHINACK[3:0] Output Cross trigger channel input acknowledge.
CTICHOUT[3:0] Output

Cross trigger channel output. Each bit represents a valid channel output:

0Channel output inactive.
1Channel output active.
CTICHOUTACK[3:0] Input Cross trigger channel output acknowledge.
CTIIRQ[N:0] Output

Active-HIGH cross trigger interrupt output:

0Interrupt not active.
1Interrupt active.
CTIIRQACK[N:0] Input Cross trigger interrupt acknowledge.
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