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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Configuration Base Address Register

Configuration Base Address Register

The CBAR characteristics are:

Holds the physical base address of the memory-mapped GIC CPU interface registers.
Usage constraints

The accessibility to the CBAR by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The CBAR is Common to the Secure and Non-secure states.
See the register summary in Table 4-98 c15 register summary.

The following figure shows the CBAR bit assignments.

Figure 4-93 CBAR bit assignments

The following table shows the CBAR bit assignments.

Table 4-130 CBAR bit assignments

Bits Name Function
[31:18] PERIPHBASE[31:18] The primary input PERIPHBASE[31:18] determines the reset value.
[17:12] - Reserved, RES0.
[11:0] PERIPHBASE[43:32] The primary input PERIPHBASE[43:32] determines the reset value.

To access the CBAR in AArch32 state, read the CP15 register with:

MRC p15, 1, <Rt>, c15, c3, 0; Read Configuration Base Address Register
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