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ARM Cortex-A72 MPCore Processor Technical Reference Manual : Configuration Base Address Register, EL1

Configuration Base Address Register, EL1

The CBAR_EL1 characteristics are:

Holds the physical base address of the memory-mapped GIC CPU interface registers.
Usage constraints

The accessibility to the CBAR_EL1 by Exception level is:

EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)

The CBAR_EL1 is:

  • Common to the Secure and Non-secure states.
  • A 64-bit register in AArch64 state.
See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.

The following figure shows the CBAR_EL1 bit assignments.

Figure 4-78 CBAR_EL1 bit assignments

The following table shows the CBAR_EL1 bit assignments.

Table 4-82 CBAR_EL1 bit assignments

Bits Name Function
[63:44] - Reserved, RES0
[43:18] PERIPHBASE The primary input PERIPHBASE[43:18] determines the reset value
[17:0] - Reserved, RES0

To access the CBAR_EL1 in AArch64 state, read the register with:

MRS <Xt>, s3_1_c15_c3_0; Read EL1 Configuration Base Address Register
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