The following figure shows the IOFPFA clocks and clock domains.
Figure 2-5 IOFPGA clocks
The bootup clock for the peripherals in the SMB_CLK domain during powerup and configuration is OSCCLK 9 on the V2M‑Juno motherboard. The clock source then switches to SMB_CLKO from the Juno SoC that becomes the master clock for the SMB_CLK domain during runtime.
Table 2-2 V2M‑Juno motherboard OSCCLK clock sources
|Clock name||Source||Default Frequency||Description|
OSCCLK 9 during powerup and configuration
SMC_CLKO during runtime
|50MHz||Reference clock for the SMB_CLK domain. This domain contains the following IOFPGA
peripherals and subsystems:
|CLK_24MHZ||CLK_24MHZ clock generator.||24MHz fixed frequency||Reference clock for the following blocks inside the
SMB_CLK clock domain:
|SMB_MCLK||MCC||50MHz||Master clock for the SMB_MCLK domain that includes the MCC and the MCC to AHB fabric in the IOFPGA.|