You copied the Doc URL to your clipboard.

IOFPGA clocks

The following figure shows the IOFPFA clocks and clock domains.

Figure 2-5 IOFPGA clocks

The bootup clock for the peripherals in the SMB_CLK domain during powerup and configuration is OSCCLK 9 on the V2M‑Juno motherboard. The clock source then switches to SMB_CLKO from the Juno SoC that becomes the master clock for the SMB_CLK domain during runtime.

Table 2-2 V2M‑Juno motherboard OSCCLK clock sources

Clock name Source Default Frequency Description

OSCCLK 9 during powerup and configuration

SMC_CLKO during runtime

50MHz Reference clock for the SMB_CLK domain. This domain contains the following IOFPGA peripherals and subsystems:
  • AHB subsystem.
  • APB subsystem.
  • PL031 Real‑Time Clock.
  • APB system registers.
  • System Bus Controllers, SBCon.
  • SP805 Watchdog Timer.
  • SP804 Dual‑Timers.
  • PL061 GPIO.
  • SP810 System Controller.
CLK_24MHZ CLK_24MHZ clock generator. 24MHz fixed frequency Reference clock for the following blocks inside the SMB_CLK clock domain:
  • PL180 MultiMedia Card Interface.
  • PL050 Keyboard and mouse interfaces.
  • Energy meters, that is, the voltage, current, power, and accumulated energy meters.
  • The clock generator that generates the 32kHz and 1MHz source clocks for the SP810 System Controller and the 1Hz clock for the PL031 Real‑Time Clock.


  • The SP810 System Controller selects 32kHz or 1MHz as the sources for TIM_CLK[3:0], the SP804 timer clocks. The powerup default is 32kHz.

    It also generates the SP805 clock, WDT_CLK.

  • The frequency of the clock 32kHz is 32.768kHz.
SMB_MCLK MCC 50MHz Master clock for the SMB_MCLK domain that includes the MCC and the MCC to AHB fabric in the IOFPGA.
Was this page helpful? Yes No