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Power control and Dynamic Voltage and Frequency Scaling (DVFS)

The V2M‑Juno motherboard provides DVFS, in addition to monitoring the voltage, current, power, temperature, and energy monitoring of the Juno SoC power domains.

The V2M‑Juno motherboard contains a Power Management IC (PMIC) that generates the V2M‑Juno motherboard and Juno SoC power supplies. The Juno SoC configures the PMIC through the System Control Processor (SCP) I2C interface during powerup or reset.

Direct control of the PMIC through the SCP interface during runtime supports voltage scaling.

Varying the Juno Arm® Development Platform SoC PLL dividers during runtime supports frequency scaling.


Arm recommends that you use this method to achieve DVFS frequency scaling, not external control of the clock generators through the V2M‑Juno motherboard SCP I2C interface.

Dedicated logic blocks in the IOFPGA contain current, voltage, power, and energy meters for the Cortex®‑A53, Cortex‑A57, Mali™‑T624 GPU and, VSYS supplies. These register addresses are in the APB Registers memory space.


The VSYS supply powers the fabric of the Juno SoC outside the Cortex‑A53, Cortex‑A57, and Mali‑T624 GPU clusters.

The following figure shows the V2M‑Juno motherboard power control and DVFS system.

Figure 2-3 Power control and DVFS system

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