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Juno SoC and V2M‑Juno motherboard clocks

The following figure shows the Juno Arm® Development Platform SoC clocks and clock domains. The figure includes the clocks that connect to the LogicTile Express daughterboard, to some of the peripherals on the V2M‑Juno motherboard, and to the IOFPGA.

Figure 2-4 Juno Arm Development Platform SoC system clocks


The following table shows the internal Juno SoC and V2M‑Juno motherboard clocks and their sources.

Table 2-1 Juno SoC clocks and their sources on the V2M‑Juno motherboard

Juno SoC clock Source Juno SoC clock default frequency Description
SYS_REF_CLK OSCCLK 0 50MHz Main system clock for the Juno SoC. Source clock for the following systems and PLLs inside the Juno SoC:
CSS main system clock:
1600MHz.
Cortex‑A57 clock (A57_PLL_CLK) maximum operating frequencies:
Underdrive: 450MHz. Nominal drive: 800MHz. Overdrive: 1.1GHz.
Cortex‑A53 clock (A53_PLL_CLK) maximum operating frequencies:
Underdrive: 450MHz. Nominal drive: 700MHz. Overdrive: 850MHz.
Mali‑T624 GPU clock (GPU_PLL_CLK) maximum operating frequencies:
Underdrive: 450MHz. Nominal drive: 600MHz. Overdrive: Not supported.
DMCCLK:
DMC-400 clock. 400MHz.
DMC_AUX_CLK:
External DMC interface on V2M‑Juno motherboard clock. 800MHz.
FAXICLK:
Fast AXI clock. 533MHz.
SAXICLK:
Slow AXI clock. 400MHz.
USBHCLK:
Primary clock for the BIU of the USB EHCI and OHCI host controllers. 160MHz.
TMIF_CLK2X:
AXI master interface reference clock in the forward direction. 123MHz.
TSIF_CLK2X:
AXI slave interface reference clock in the reverse direction. 123MHz.
APBCLK:
Clocks the SMB_CLK domain in the IOFPGA. 100MHz.
TRACE_CLKA, TRACE_CLKB:
145.45MHz.
AON_REF_CLK OSCCLK 1 50MHz Source clock for the I2C clock generator and reference clock for the SCP PLL inside the Juno SoC. This derives the following clock:
SCPHCLK:
SCP subsystem and AHB expansion area clock.
PXL_REF_CLK OSCCLK 2 50MHz Reference clock for the HDLCD PLL inside the Juno SoC. This generates PXL_PLL_CLK, 23.75MHz.
HDLCDC0_PXL_CLK_OUT HDLCD0 in Juno SoC 165MHz Pixel clock to HDMI PHY 0 on the V2M‑Juno motherboard. The default operating frequency of the PHY, 165MHz, is also the maximum operating frequency.
HDLCDC1_PXL_CLK_OUT HDLCD1 in Juno SoC 165MHz Pixel clock to HDMI PHY 1 on the V2M‑Juno motherboard. The default operating frequency of the PHY, 165MHz, is also the maximum operating frequency.
S32K_CLK CLK_32K clock generator 32.768kHz Fixed frequency real‑time clock. Provides a real‑time private time domain for the SCP that uses it to implement very low‑power sleep modes.
I2S_CLK OSCCLK 4 2.11MHz Integrated-IC sound clock. Clocks the I2S audio bus.
I2C_CLK OSCCLK 1 50MHz Clocks the I2C control bus.
UART_CLK OSCCLK 11 7.3728MHz Clocks the UART interface.
TCK Trace connector 25MHz From external trace port analyzer. Clocks the Trace debug system.
ULPI_CLK USB2 2.0 xtal clock generator. 60MHz Fixed frequency clock. Clocks the USB 2.0 Transceiver Macrocell Interface Low-Pin Interface (ULPI) from the off‑chip PHY.
USB_CLK48 CLK_48M clock generator. 48MHz Primary clock input to the USB controller.
SMC_MCLK OSCLK 5 50MHz Clocks the PL354 Static Memory Controller (SMC) interface.
SMC_FB_CLK IOFPGA 50MHz Feedback clock from IOFPGA to read data back into the PL354 in synchronous mode. The SMC uses this to adjust timing.
SMC_CLKO OSCLK 5 50MHz Derived from SMC_MCLK. Exported from Juno SoC to the SMB timing adjust block in the IOFPGA.
CFG_CLK MCC. 10MHz Serial Configuration Controller (SCC) serial interface clock.
TMIF_CLKI TLX-400 Thin Links AXI slave interface in FPGA on LogicTile fitted in daughterboard site. 61.5MHz Clock in the receive direction to the TLX-400 Thin Links AXI master interface on the Juno SoC.
TMIF_CLKO TLX-400 Thin Links AXI master interface reference clock generator in Juno SoC. 61.5MHz Clock in the transmit direction from the TLX-400 Thin Links AXI master interface on the Juno SoC.
TSIF_CLKI TLX-400 Thin Links AXI master interface in FPGA on LogicTile fitted in daughterboard site. 61.5MHz Clock in the receive direction to the TLX-400 Thin Links AXI slave interface on the Juno SoC.
TSIF_CLKO TLX-400 Thin Links AXI slave interface reference clock generator in Juno SoC. 61.5MHz Clock in the transmit direction from the TLX-400 Thin Links AXI slave interface on the Juno SoC.

The MCC uses the board.txt configuration file in the microSD card to set the frequency of the board clock generators. You can adjust these default clock frequencies by editing this file. You can also adjust the board clocks during runtime by using the SYS_CFG register interface.

The Juno SoC has internal PLLs and clock generators that generate clocks to drive the Juno SoC internal systems.

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