The Juno Arm® Development Platform SoC implements a GIC-400 generic interrupt controller with 13 external interrupts:
- Seven of the external interrupts connect to IOFPGA peripherals.
- One external interrupt connects to the SMC 10/100 Ethernet.
- One external interrupt connects to the MCC.
- One external interrupt connects to the LogicTile daughterboard site.
- The other three external interrupts are reserved.
NoteThe prototype board provides an SMC USB 2.0 interface that the production board does not provide. The SMC USB 2.0 uses one of the reserved interrupts leaving two external interrupts as reserved on the prototype board.
The MCC generates its interrupt when you press the ON/OFF/Soft Reset push button. All interrupts connect to the GIC-400 interrupt controller in the Juno Arm Development Platform SoC through the IOFPGA.
The following figure shows an overview of the external interrupt signals from the V2M‑Juno motherboard peripherals to the GIC-400 interrupt controller in the Juno Arm Development Platform SoC.
Figure 2-12 Juno Arm Development Platform SoC interrupts overview
The following table shows the mapping of the external interrupt signals to the GIC-400 controller in the Juno Arm Development Platform SoC. It lists the sources of the interrupts that originate in the V2M‑Juno motherboard or the LogicTile Express fitted in the daughterboard site.
Table 2-5 External interrupt signals to Juno SoC
|Interrupt ID||GIC IRQ ID||Motherboard signal name||Source|
|96-99||64-67||-||Juno Arm Development Platform SoC internal peripherals and systems.|
|103-191||71-159||-||Juno Arm Development Platform SoC internal peripherals and systems.|
|192||160||SB_IRQ||IOFPGA-SMC 10/100 Ethernet.|
|194||162||SB_IRQ||IOFPGA-PL180 user microsSD card.|
|195||163||SB_IRQ||IOFPGA-PL061 GPIO (0) and GPIO (1) used for additional user key entry.|
|197||165||SB_IRQ||IOFPGA-PL050 KMI interface.|
|198||166||SB_IRQ||IOFPGA-SP804 Dual-timer (0-1) and SP804 dual-timer (2-3).|
|199||167||SB_IRQ||IOFPGA:APB system registers from SYS_MISC[SWINT] Register.|
|200||168||SB_IRQ||LogicTile FPGA daughterboard. Interrupt from FPGA on LogicTile daughterboard.|
|201||169||SB_IRQ||MCC-Interrupt generated by pressing the ON/OFF/Soft Reset push button.|
|202-223||170-191||-||Juno Arm Development Platform SoC internal peripherals and systems.|
See the Juno Arm® Development Platform SoC Technical Reference Manual (Revision r0p0) for information on the interrupts from the systems in the Juno Arm Development Platform SoC.
See Overview of the prototype V2M‑Juno motherboard for information on interrupts SB_IRQ[4:3] on the prototype V2M‑Juno motherboard.