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Juno Arm® Development Platform SoC

This section provides an overview of the components of the Juno Arm® Development Platform SoC. This development chip, or Juno SoC, provides a dual‑core Cortex®‑A57 cluster, a quad‑coreCortex‑A53 cluster, a quad‑core Mali™‑T624 graphics cluster, interfaces, on‑chip peripherals, and internal network connect.

The following figure shows the architecture of the Juno Arm Development Platform SoC.

Figure 2-2 Architecture of the Juno Arm Development Platform SoC


The Juno Arm Development Platform SoC contains the following components and interfaces:

  • Dual‑core Cortex‑A57 cluster:
    • 2MB L2 cache.
    • NEON™ and FPU.
    • Underdrive: Maximum operating frequency: 450MHz.
    • Nominal drive: Maximum operating frequency: 800MHz.
    • Overdrive: Maximum operating frequency: 1.1GHz.
  • Quad‑core Cortex‑A53 cluster:
    • 1MB L2 cache.
    • NEON and Floating Point Unit (FPU).
    • Underdrive: Maximum operating frequency: 450MHz
    • Nominal drive: Maximum operating frequency: 700MHz.
    • Overdrive: Maximum operating frequency: 850MHz.
  • Mali‑T624 quad‑core GPU cluster:
    • Underdrive: Maximum operating frequency: 450MHz.
    • Nominal drive: Maximum operating frequency: 600MHz.
    • Overdrive: Maximum operating frequency: Not supported.
  • Internal AXI subsystem operating at up to 533MHz.
  • Dual Arm HDLCD Display Controllers that support HDMI 1.4a up to 1080p.
  • Dual DDR3L PHY and 32‑bit DDR3L interfaces.
  • Thin Links AXI master and slave interfaces to the LogicTile site. At the default clock frequency of 61.5MHz, the operating speeds are:
    • Master interface: 68MBps in the forward direction and 78MBps in the reverse direction.

    • Slave interface: 246MBps in the forward direction and 305MBps in the reverse direction.

      Note

      • The forward direction is from master to slave and the reverse direction is from slave to master.
      • Expansion AXI over Thin Links provides a 256MB window.
  • USB 2.0 Host Controller. This is a 480Mbps ULPI interface to off‑chip PHY.
  • PL354 Static Memory Controller (SMC).
  • PL330 Direct Memory Access (DMA) controller.
  • CoreSight™ Processor debug (P‑JTAG) and Trace.
  • APB subsystem:
    • Dual‑UART.
    • I2S 4‑channel stereo audio.
    • Power, Voltage, and Temperature (PVT) monitoring of Juno Arm Development Platform SoC.
    • Non-volatile counter. A real‑time clock that retains its stored value after powerdown.
    • System Control Processor (SCP). The SCP is a Cortex-M3 processor integrated into the Juno Arm Development Platform SoC. It initiates the system architecture and pre‑load memory at powerup and performs power management and system control functions during runtime.
    • I2C. This connects to HDMI controllers, the UART transceiver, and other components on the V2M‑Juno motherboard.
    • Secure I2C. Connects to the Secure Keyboard.
    • Keys. Encryption keys for signing software.
    • Random-number generator. Operates with the encryption keys when validating software.
    • System override registers that enable you to override various aspects of the Juno Arm Development Platform SoC.

See the Juno Arm® Development Platform SoC Technical Reference Manual (Revision r0p0) for more information. This document lists, in the Additional Reading section, references to Arm IP, such as the PL011 for example, inside the Juno SoC.

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