You copied the Doc URL to your clipboard.

Overview of Thin Links AXI master and slave interfaces

The Juno Arm® Development Platform SoC contains one AXI master interface and one slave AXI interface that connect to the FPGA in the LogicTile Express daughterboard fitted in the V2M‑Juno motherboard tile site. A Thin Links TLX-400 interface compresses the AXI master and slave interfaces to reduce the pin count.

The width of the TLX-400 slave interface on the Juno Arm Development Platform SoC is greater than the width of the master interface.

The default Thin Links clock frequency of 61.5MHz gives the following operating speeds:

  • Juno SoC master interface:
    • Forward direction, that is, from the Juno SoC to the FPGA: 68MBps.
    • Reverse direction, that is, from the FPGA to the Juno SoC: 78MBps.
  • Juno SoC slave interface:
    • Forward direction, that is, from the FPGA to the Juno SoC: 246MBps.
    • Reverse direction, that is, from the Juno SoC to the FPGA: 305MBps.

Note

Arm recommends that you operate the Thin Links interfaces at the default speeds. See Contents of the SITE1 directory for an example board.txt configuration file that sets the Thin Links clocks to 61.5MHz.

The following table shows the Thin Links timing requirements.

Table 2-3 Thin Links timing requirements

Symbol Min Max Description
Tsu 1.2ns - Input data parameter. Minimum data setup time before clock edge.
Th 1.0ns - Input data parameter. Minimum data hold time after clock edge.
Tcomin -2.5ns -

Tcomin is relative to clock edge.

Data is available on the bus between Tcomin and Tcomax.

Tcomax 2.5ns -

Tcomax is relative to clock edge.

Data is available on the bus between Tcomin and Tcomax.

Note

Any Versatile™ Express LogicTile daughterboard fitted in the tile site that implements an Arm application note meets these timing requirements.

Any design that you implement in a Versatile Express LogicTile daughterboard, or in your own daughterboard, must meet these timing requirements.

Was this page helpful? Yes No